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description these small outline high cmr, high speed, logic gate opto coup lers are single channel devices in a ?ve lead miniature foot print. they are electrically equivalent to the following avago optocouplers (except there is no output enable feature): so-5 package standard dip so-8 package HCPL-M600 6n137 hcpl-0600 hcpl-m601 hcpl-2601 hcpl-0601 hcpl-m611 hcpl-2611 hcpl-0611 the so-5 jedec registered (mo-155) package outline does not require through holes in a pcb. this package occupies approximately one fourth the footprint area of the standard dual-in-line package. the lead pro?le is de- signed to be com patible with standard surface mount processes. the HCPL-M600/01/11 optically coupled gates combine a gaasp light emitting diode and an integrated high gain photon detector. the output of the detector i.c. is an open-collector schottky-clamped transistor. the internal shield provides a guaranteed common mode transient immunity speci?cation of 5,000 v/s for the hcpl-m601, and 10,000 v/s for the hcpl-m611. this unique design provides maximum ac and dc circuit isolation while achieving ttl compatibility. the optocou- pler ac and dc operational param et ers are guaranteed from C40c to 85c allowing trouble free system performance. HCPL-M600, hcpl-m601, hcpl-m611 small outline, 5 lead, high cmr, high speed, logic gate optocouplers data sheet features surface mountable very small, low pro?le jedec registered package outline compatible with infrared vapor phase re?ow and wave soldering processes internal shield for high common mode rejection (cmr) hcpl-m601: 10,000 v/s at v cm = 50 v hcpl-m611: 15,000 v/s at v cm = 1000 v high speed: 10 mbd lsttl/ttl compatible low input current capability: 5 ma guaranteed ac and dc performance over temperature: C40c to 85c safety and regulatory approvals: - ul recognized: 3750 vac for 1 min. per u.l. (file no. 55361) - csa component acceptance notice #5 - iec/en/din en 60747-5-2 approved for hcpl-m601/ m611 option 060. lead free option applications isolated line receiver simplex/multiplex data transmission computer-peripheral interface microprocessor system interface digital isolation for a/d, d/a conversion switching power supply instrument input/output isolation ground loop elimination pulse transformer replacement caution: the small device geometries inherent to the design of this bipolar component increase the component's suscep ti bility to damage from electrostatic discharge (esd). it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant ro h s 6 f u lly comp l iant options a v ai l a bl e ; -xxxe denotes a l ead -f ree product
2 the so-5 jedec registered (mo-155) package outline does not require through holes in a pcb. this package occupies approximately one fourth the footprint area of the standard dual-in-line package. the lead pro?le is de- signed to be com patible with standard surface mount processes. the HCPL-M600/01/11 optically coupled gates combine a gaasp light emitting diode and an integrated high gain photon detector. the output of the detector i.c. is an open-collector schottky-clamped transistor. the internal shield provides a guaranteed common mode transient immunity speci?cation of 5,000 v/s for the hcpl-m601, and 10,000 v/s for the hcpl-m611. this unique design provides maximum ac and dc circuit isolation while achieving ttl compatibility. the opto- coupler ac and dc operational param eters are guaran- teed from -40c to 85c allowing trouble free system performance. the HCPL-M600/01/11 are suitable for high speed logic interfacing, input/output bu?ering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. ordering information hcpl-xxxx is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount gull wing tape& reel ul 5000 vrms/ 1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant HCPL-M600 -000e no option so-5 x 100 per tube -500e #500 x x 1500 per reel hcpl-m601 hcpl-m611 -000e no option so-5 x 100 per tube -500e #500 x x 1500 per reel -560e - x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the op- tion column to form an order entry. combination of option 020 and option 060 is not available. example 1: HCPL-M600-500e to order product of surface mount so-5 package in tape and reel packaging with rohs compliant. example 2: hcpl-m601 to order product of surface mount so-5 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15 th july 2001 and rohs compliant option will use -xxxe.
3 outline drawing (jedec mo-155) land pattern recommendation schematic hcpl-m601/11 shield 6 5 4 1 3 use of a 0.1 f bypass capacitor must be connected between pins 6 and 4 (see note 1). i f i cc v cc v o gnd i o + C truth table (positive logic) led on off output l h mxxx xxx 6 5 4 3 1 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) v cc v out gnd cathode anode 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.216 0.038 (0.0085 0.0015) 0.71 (0.028) min. 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold flash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. 7 max. max. lead coplanarity = 0.102 (0.004) 8.27 (0.325) 2.0 (0.080) 2.5 (0.10) 1.3 (0.05) 0.64 (0.025) 4.4 (0.17) regulatory information the HCPL-M600, hcpl-m601 and hcpl-m611 are approved by the following organizations: iec/en/din en 60747-5-5 (option 060 only) for hcpl-m601 and hcpl-m611 ul approval under ul 1577, component recognition pro- gram up to v iso = 3750 v rms . csa approval under csa component acceptance notice #5, file ca 88324.
4 insulation and safety related speci?cations parameter symbol value units conditions minimum external air gap (external clearance) l(101) 5 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (external creepage) l(102) 5 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti 175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) iec/en/din en 60747-5-5 insulation characteristics* (option 060) description symbol characteristic unit installation classi?cation per din vde 0110/39, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms i C iv i C iii climatic classi?cation 55/85/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 560 vpeak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with tm=1 sec, partial discharge < 5 pc v pr 1050 vpeak input to output test voltage, method a* v iorm x 1.5=v pr , type and sample test, tm=60 sec, partial discharge < 5 pc v pr 840 vpeak highest allowable overvoltage (transient overvoltage t ini =10 sec) v iotm 6000 vpeak safety-limiting values C maximum values allowed in the event of a failure. case temperature input current** output power** t s i s, input p s, output 150 150 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/ en/din en 60747-5-2) for a detailed description of method a and method b partial discharge test pro?les. ** refer to the following ?gure for dependence of p s and i s on ambient temperature. recommended operating conditions parameter symbol min. max. units input current, low level i fl * 0 250 a input current, high level i fh ** 5 15 ma supply voltage, output v cc 4.5 5.5 v fan out (r l = 1 k) n 5 ttl loads output pull-up resistor r l 330 4,000 operating temperature t a -40 85 c * the o? condition can also be guaranteed by ensuring that v f (o? ) 0.8 volts. ** the initial switching threshold is 5ma or less. it is recommended that 6.3ma to 10ma be used for best performance and to pe rmit at least a 20% led degradation guardband.
5 absolute maximum ratings (no derating required up to 85c) parameter abs. max. storage temperature -55c to +125c operating temperature -40c to +85c forward input current - i f (see note 2) 20 ma reverse input voltage - v r 5 v supply voltage - v cc (1 minute maximum) 7 v output collector current - i o 50 ma output collector power dissipation 85 mw output collector voltage - v o (selection for higher output voltages up to 20 v is available) 7 v infrared and vapor phase re?ow temperature see below solder re?ow thermal pro?le recommended pb-free ir pro?le note: non-halide ?ux should be used. note: non-halide ?ux should be used. 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp. 245c peak temp. 240c peak temp. 230c soldering time 200c preheating time 150c, 90 + 30 sec. 2.5c 0.5c/sec. 3c + 1c/C0.5c tight typical loose room temperature preheating rate 3c + 1c/C0.5c/sec. reflow heating rate 2.5c 0.5c/sec. 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c
6 insulation related speci?cations parameter symbol value units conditions min. external air gap l(io1) 5 mm measured from input terminals (clearance) to output terminals min. external tracking path l(io2) 5 mm measured from input terminals (creepage) to output terminals min. internal plastic gap 0.08 mm through insulation distance (clearance) conductor to conductor tracking resistance cti 175 v din iec 112/vde 0303 part 1 isolation group (per din vde 0109) iiia material group din vde 0109 electrical speci?cations over recommended temperature (t a = -40c to 85c) unless otherwise speci?ed. (see note 1.) parameter symbol min. typ.* max. units test conditions fig. note input threshold i th 2 5 ma v cc = 5.5 v, i o 13 ma, 13 current v o = 0.6 v high level output i oh 5.5 100 a v cc = 5.5 v, v o = 5.5 v 1 current i f = 250 a low level output v ol 0.4 0.6 v v cc = 5.5 v, i f = 5 ma, 2, 4, voltage i ol (sinking) = 13 ma 5, 13 high level supply i cch 4 7.5 ma v cc = 5.5 v, i f = 0 ma, current low level supply i ccl 6 10.5 ma v cc = 5.5 v, i f = 10 ma, current input forward v f 1.4 1.75 v t a = 25c, i f =10 ma 3 voltage 1.5 1.3 1.85 i f = 10 ma input reverse bv r 5 i r = 10 a breakdown voltage input capacitance c in 60 pf v f = 0v, f = 1 mhz input diode ?v f /?t a -1.6 mv/c i f = 10 ma 12 temperature coe?cient input-output v iso 3750 v rms rh 50%, t = 1 min. 3, 4 insulation resistance r i-o 10 12 v i-o = 500 v 3 (input-output) capacitance c i-o 0.6 pf f = 1 mhz 3 (input-output) *all typicals at t a = 25c, v cc = 5 v.
7 notes: 1. bypassing of the power supply line is required with a 0.1 f ceramic disc capacitor adjacent to each optocoupler. the total lead length be- tween both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. peaking circuits may produce transient input currents up to 50 ma, 50 ns maximum pulse width, provided average current does not exceed 20 ma. 3. device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 4. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detec- tion current limit, i i-o 5 a). 5. the t plh propagation delay is measured from 3.75 ma point on the falling edge of the input pulse to the 1.5 v point on the rising edge of the output pulse. 6. the t phl propagation delay is measured from 3.75 ma point on the rising edge of the input pulse to the 1.5 v point on the falling edge of the output pulse. 7. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state ( i.e., v out > 2.0 v). 8. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i .e., v out > 0.8 v). 9. for sinusoidal voltages, (|dv cm |/dt) max = f cm v cm(p-p) . 10. see application section; propagation delay, pulse-width distortion and propagation delay skew for more information. 11. t psk is equal to the worst case di?er ence in t phl and/or t plh that will be seen between units at any given temperature within the worst case operating condition range. switching speci?cations over recommended temperature (t a = -40c to 85c), v cc = 5 v, i f = 7.5 ma unless otherwise speci?ed. device parameter symbol hcpl- min. typ.* max. unit test conditions fig. note propagation t plh 20 48 75 ns t a = 25c r l = 350 6, 7 5 delay time to high 100 c l = 15 pf 8 output level propagation t phl 25 50 75 t a = 25c 6, 7 6 delay time to low 100 8 output level propagation t psk 40 10, delay skew 11 pulse width |t phl - t plh | 3.5 35 9 10 distortion output rise t rise 24 time 10 (10%-90%) output fall t fall 10 time 10 (10%-90%) common |cm h | m600 10,000 v/s v cm = 10 v v o(min) = 2 v 11 7, 9 m601 5,000 10,000 v cm = 50 v m611 10,000 15,000 v cm = 1000 v common |cm h | m600 10,000 v cm = 10 v v o(max) = 0.8 v 11 8, 9 m601 5,000 10,000 v cm = 50 v m611 10,000 15,000 v cm = 1000 v *all typicals at t a = 25c, v cc = 5 v. mode transient immunity at high output level mode transient immunity at low output level r l = 350 i f = 7.5 ma t a = 25c r l = 350 i f = 0 ma t a = 25c
8 figure 5. low level output current vs. temperature. figure 4. output voltage vs. forward input current. figure 1. high level output current vs. temperature. figure 2. lo w level output voltage vs. temperature. figure 3. input diode fo rward characteristic. figure 6. test circuit for t phl and t plh . i oh C high level output current C a -60 0 t a C temperature C c 100 10 15 -20 5 20 v cc = 5.5 v v o = 5.5 v i f = 250 a 60 -40 0 40 80 v cc = 5.5 v i f = 5.0 ma 0.5 0.4 -60 -20 20 60 100 t a C temperature C c 0.3 80 40 0 -40 0.1 v ol C low level output voltage C v 0.2 i o = 16 ma i o = 12.8 ma i o = 9.6 ma i o = 6.4 ma v f C forward voltage C volts 10 0.1 0.01 1.10 1.20 1.30 1.40 i f C forward current C ma 1.60 1.50 1.0 0.001 100 i f v f + t a = 25c C 1 6 2 3 4 5 1234 5 6 i f C forward input current C ma r l = 350 r l = 1 k r l = 4 k 0 0 v cc = 5 v t a = 25 c v o C output voltage C v i ol C low level output current C ma -60 0 t a C temperature C c 100 60 80 -20 20 20 v cc = 5.0 v v ol = 0.6 v 60 -40 0 40 80 40 i f = 10 ma, 15 ma i f = 5.0 ma output v o monitoring node 1.5 v t plh t phl i f input v o output i f = 7.5 ma i f = 3.75 ma +5 v i f r l r m 0.1f bypass *c l *c l is approximately 15 pf which includes probe and stray wiring capacitance. input monitoring node pulse gen. z o = 50 t f = t r = 5 ns v cc gnd 1 3 6 5 4
9 figure 12. temperature coe?cient for forward voltage vs. input current. figure 10. rise and fall time vs. temperature. figure 9. pulse width distortion vs. temperature. figure 8. propagation delay vs. pulse input current. figure 7. propagation delay vs. temperature. figure 11. test circuit for common mode transient immunity and typical waveforms. v cc = 5.0 v i f = 7.5 ma 100 80 -60 -20 20 60 100 t a C temperature C c 60 80 40 0 -40 0 t p C propagation delay C ns 40 20 t plh , r l = 4 k t plh , r l = 1 k t plh , r l = 350 t phl , r l = 350 1 k 4 k v cc = 5.0 v t a = 25c 105 90 5913 i f C pulse input current C ma 75 15 11 7 30 t p C propagation delay C ns 60 45 t plh , r l = 4 k t plh , r l = 1 k t plh , r l = 350 t phl , r l = 350 1 k 4 k v cc = 5.0 v i f = 7.5 ma 40 30 -20 20 60 100 t a C temperature C c 20 80 40 0 -40 pwd C pulse width distortion C ns 10 r l = 350 k r l = 1 k r l = 4 k 0 -60 -10 t r , t f C rise, fall time C ns -60 0 t a C temperature C c 100 300 -20 40 20 60 -40 0 40 80 60 290 20 v cc = 5.0 v i f = 7.5 ma r l = 4 k r l = 1 k r l = 350 , 1 k , 4 k t rise t fall r l = 350 dvf/ dt C forward voltage temperature coefficient C mv/c 0.1 1 10 100 i f C pulse input current C ma -1.4 -2.2 -2.0 -1.8 -1.6 -1.2 -2.4 v o 0.5 v v o (min.) 5 v 0 v switch at a: i f = 0 ma switch at b: i f = 7.5 ma v cm cm h cm l v o (max.) v cm (peak) v o +5 v 0.1 f bypass + _ 350 v ff 1 3 6 5 4 b a output v o monitoring node i f pulse generator z o = 50 v cc gnd
propagation delay, pulse-width distortion and propagation delay skew propagation delay is a ?gure of merit which describes how quickly a logic signal propagates through a sys- tem. the propaga tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input sig- nal to propagate to the output, causing the output to change from high to low (see figure 7). pulse-width distortion (pwd) results when t plh and t phl di?er in value. pwd is de?ned as the di?erence between t plh and t phl and often determines the maxi mum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typi- cally, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact ?gure depends on the par- ticular appli cation (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important param- eter to consider in parallel data appli cations where synchroniza tion of signals on parallel data lines is a con- cern. if the parallel data is being sent through a group of optocouplers, di?er ences in propagation delays will cause the data to arrive at the outputs of the optocou- plers at di?erent times. if this di?erence in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the op- tocouplers. propagation delay skew is de?ned as the di?erence be- tween the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and op- erating tempera ture). as illustrated in figure 15, if the in- puts of a group of optocouplers are switched either on or off at the same time, t psk is the di?erence between the shortest propagation delay, either t plh or t phl , and the longest propaga tion delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through opto- couplers. the ?gure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an op- tocoupler. figure 16 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data out- puts have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel applica- tion is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncer- tainty in the rest of the circuit does not cause a prob- lem. the t psk speci?ed optocouplers o?er the advantages of guaranteed speci?cations for propagation delays, pulse- width distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges.
figure 15. illustration of propagation delay skew C t psk . figure 13. input threshold current vs. temperature. figure 14. recommended ttl/lsttl to ttl/lsttl interface circuit. figure 16. parallel data transmission example. i th C input threshold current C ma -60 0 t a C temperature C c 100 4 5 -20 2 20 60 -40 0 40 80 3 v cc = 5.0 v v o = 0.6 v 1 r l = 4 k r l = 1 k r l = 350 6 v cc 1 gnd 1 470 shield * diode d1 (1n916 or equivalent) is not required for units with open collector output. 6 5 4 390 0.1 f bypass gnd 2 v cc 2 1 3 *d1 5 v 5 v i f v f 2 1 50% 1.5 v i f v o 50% i f v o t psk 1.5 v data t psk inputs clock data outputs clock t psk for product in f ormation and a complete list o f distri b utors, please go to our we b site: www.avagotech.com a v ago, a v ago technologies, and the a logo are trademarks o f a v ago technologies in the united states and other countries. data su b ject to change. cop y right ? 2005 - 2010 a v ago technologies. all rights reser v ed. o b soletes av01 - 05 6 2en av02 - 0941en - fe b ruar y 23, 2010

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